1. Field of the Invention
This invention relates to a semiconductor device, a liquid crystal display device, a process for a semiconductor device and a process for a liquid crystal display device, in particular to a semiconductor device, a liquid crystal display device, a process for a semiconductor device and a process for a liquid crystal display device which include field effect transistors having an LDD (Lightly Doped Drain) structure.
2. Description of the Background Art
Conventionally, a liquid crystal display device, which utilizes thin film field effect transistors formed on a glass substrate, has been known as one of liquid crystal display devices. A glass substrate where thin film field effect transistors are formed in such a liquid crystal display device is shown in FIG. 47. FIG. 47 is a cross section diagram showing a conventional liquid crystal display device. Referring to FIG. 47, a liquid crystal display device is described.
Referring to FIG. 47, an n type thin film field effect transistor 119 and a p type thin film field effect transistor 120 are formed in a drive circuit region on a glass substrate 101 in a liquid crystal display device. In addition, a capacitor 121 and a thin film field effect transistors 122 for a pixel are formed in a display pixel region.
In the drive circuit region, a base film 102 is formed on the glass substrate 101. A silicon oxide film is used for this base film n+ type impurity regions 103a, 103b, nxe2x88x92 type impurity regions 104a, 104b and a channel region 106a are formed on the base film 102 by using the same semiconductor film. A gate insulating film 107a is formed on the channel region 106a. A gate electrode 108a is formed on the gate insulating film 107a. The source/drain regions are formed of n+ type impurity regions 103a, 103b and nxe2x88x92 type impurity regions 104a, 104b. The n type thin film field effect transistor 119 is formed of those n+ type impurity regions 103a, 103b, nxe2x88x92 type impurity regions 104a, 104b, channel region 106a, gate insulating film 107a and gate electrode 108a. 
In addition, p type impurity regions 105a, 105b and a channel region 106b are formed on the base film 102 by using the same semiconductor film. A gate insulating film 107b is formed on the channel region 106b. A gate electrode 108b is formed on the gate insulating film 107b. A p type thin film field effect transistor 120 is formed of those p type impurity regions 105a, 105b, channel region 106b, gate insulating film 107b and gate electrode 108b. An interlayer insulating film 110 is formed on those n type thin film field effect transistor 119 and p type thin film field effect transistor 120. In the regions located above the n+ type impurity regions 103a, 103b and the p type impurity regions 105a, 105b, contact holes 111a to 111d are formed in the interlayer insulating film 110. Metal wires 112a to 112d are formed so as to extend from the inside of the contact holes 111a to 111d to the upper surface of the interlayer insulating film 110. A passivation film (not shown) is formed on the metal wires 112a to 112d. A flatting film 113 is formed on the passivation film.
In the display pixel region, a capacitor electrode 109 is formed on the base film 102. Another capacitor electrode 108e is formed above the capacitor electrode 109 via an insulating film 107e as the dielectric film. A capacitor 121 is formed of these capacitor electrodes 109, 108e and insulating film 107e. An n+ type impurity region 103c is formed, as the conductive region, on the base film 102 so as to adjoin the capacitor electrode 109. In addition, n+ type impurity regions 103d to 103f, nxe2x88x92 type impurity regions 104d to 104g and channel regions 106c, 106d are formed on the base film 102 by using the same semiconductor film. Gate insulating films 107c, 107d are formed on the channel regions 106c, 106d, respectively. Gate electrodes 108c and 108d are formed on the gate insulating films 107c, 107d, respectively. In this way, one thin film field effect transistor is formed of the n+ type impurity regions 103d, 103e, the nxe2x88x92 type impurity regions 104d, 104e, the channel region 106c, the gate insulating film 107c and the gate electrode 108c. In addition, another thin film field effect transistor is formed of the n+ type impurity regions 103e, 103f, the nxe2x88x92 type impurity regions 104f, 104g, the channel region 106d, the gate insulating film 107d and the gate electrode 108d. The thin film field effect transistors 122 for pixels include those two thin film field effect transistors.
An interlayer insulating film 110 is formed on the capacitor 121 and the thin film field effect transistors 122 for a pixel. In the regions located above the n+ type impurity regions 103c, 103d and 103f, contact holes 111e to 111g are formed in the interlayer insulating film 110. Metal wires 112e and 112f are formed so as to extend from the inside of the contact holes 111e to 111g to the upper surface of the interlayer insulating film 110. A passivation film (not shown) is formed on the metal wires 112e and 112f. A flatting film 113 is formed on the passivation film. In the region located above the metal wire 112e, a contact hole 114 is formed in the flatting film 113 and the passivation film. A pixel electrode 115 is formed so as to extend from the inside of the contact hole 114 to the upper surface of the flatting film 113 by using ITO or the like.
FIGS. 48 to 51 are cross section diagrams for describing a process for the liquid crystal display device as shown in FIG. 47. Referring to FIGS. 48 to 51, a process for a liquid crystal display device is described.
First, a base film 102 such as a silicon oxide film is formed on a glass substrate 101. An amorphous silicon film is formed on this base film 102. A polysilicon film is formed by annealing this amorphous silicon film using a laser or the like. A resist film is formed on this polysilicon film. A channel pattern is formed by carrying out an exposure to light and development processing on this resist film. Then, by using, as a mask, the resist film where the channel pattern is formed, the polysilicon film is etched so as to form polysilicon films 127a to 127c (see FIG. 48) and polysilicon film to be a capacitor electrode. After that, the resist film is removed. By implanting conductive impurities into the polysilicon film to be the capacitor electrode, a conductive film 128 (see FIG. 48) is formed. An insulating film to be a gate insulating film is formed on the polysilicon films 127a to 127c and the conductive film 128. A conductive film is formed on this insulating film. A resist film is formed on this conductive film. A gate pattern is formed in the resist film by carrying out exposure to light and development processing. By using, as a mask, the resist film where the gate pattern is formed, gate electrodes 108a to 108d (see FIG. 48) and a capacitor electrode 108e (see FIG. 48) are formed by carrying out wet etching. After that, the resist film is removed. Then, by using the gate electrodes 108a to 108d and the capacitor electrode 108e as a mask, the insulating film is etched so as to form the gate insulating film 107a to 107b (see FIG. 48) and the insulating film 107e (see FIG. 48) as the dielectric film. In this way, a structure as shown in FIG. 48 is gained.
After that, as shown in FIG. 49, a resist film 130b is formed so as to cover the region where the p type thin film field effect transistor 120 (see FIG. 47) is to be formed and at the same time resist film 130a, 130c and 130d is formed which becomes a mask for forming the n+ type impurity regions 103a to 103f. Then, phosphorus (P) ions 133 as impurity ions are implanted into predetermined regions in the polysilicon films 127a to 127c (see FIG. 48). In this manner, the n+ type impurity regions 103a to 103f are formed. After that, the resist films 130a to 130d are removed.
Next, as shown in FIG. 50, phosphorous ions 134 are implanted into predetermined regions under the condition where no resist film exists and, thereby, nxe2x88x92 type impurity regions 104a, 104b, 104d to 104g are formed.
Next, as shown in FIG. 51, resist films 135a to 135c are formed in the regions other than the regions where the p type thin film field effect transistor 120 (see FIG. 47) is to be formed. Then, boron (B) ions 136 are implanted by using the gate electrode 108b as a mask and, thereby, p type impurity regions 105a, 105b and channel region 106b are formed. After that, the resist films 135a to 135c are removed.
After this, an interlayer insulating film 110 (see FIG. 47) is formed. A resist pattern is formed on this interlayer insulating film 110. The interlayer insulating film 110 is partially etched and removed by using this resist pattern as a mask and, thereby, contact holes 111a to 111g (see FIG. 47) are formed. After that, the resist pattern is removed. Then, after carrying out a cleaning process, a metal layer which is processed to become metal wires 112a to 112f is formed so as to extend from the inside of the contact holes 111a to 111g to the upper surface of the interlayer insulating film 110. A resist pattern is formed on this metal layer. The metal film is partially removed by carrying out wet etching using this resist pattern as a mask. In this manner, the metal wires 112a to 112f (see FIG. 47) are formed. After that, the resist pattern is removed. A passivation film 113 (see FIG. 47) is formed on the metal wires 112a to 112f. After flatting the upper surface of the passivation film 113, a contact hole 114 (see FIG. 47) is formed in this passivation film 113. A transparent conductive film is formed so as to extend from the inside of the contact hole 114 to the upper surface of the passivation film 113. A resist film wherein a pixel pattern is formed on this transparent conductive film. By using this resist film as a mask the transparent conductive film is partially removed through wet etching so as to form a pixel electrode 115 (see FIG. 47). After that, the resist film is removed.
In this manner, a liquid crystal display device as shown in FIG. 47 can be gained.
In the conventional process for a liquid crystal display device as described above, the problem arises as follows. That is to say, in the step as shown in FIG. 49, the positions or the size of the nxe2x88x92 type impurity regions 104a, 104b (see FIG. 50) vary depending in the relative positioning relationship with the resist film 130a and the gate electrode 108a when noticing, for example, the region in which the n type thin film field effect transistor 119 (see FIG. 47) is to be formed. This point is described in more detail referring to FIGS. 52 and 53.
FIGS. 52 and 53 are diagrams for describing a conventional problem, which are partially enlarged cross section diagrams of the region wherein a resist film 130a is formed in the step as shown in FIG. 49.
Referring to FIG. 52, in the case that the relative positional relationship is shifted from the set position between the gate electrode 108a and the resist film 130a (the position of the resist film 130a is shifted either to the right or to the left), the respective sizes of the finally formed nxe2x88x92 type impurity regions 104a and 104b vary as shown in FIG. 52. In this manner, in the case that the sizes of the nxe2x88x92 type impurity regions 104a and 104b on the right and on the left are different, the electric property of the formed n type thin film field effect transistor 119 fluctuates from the designed value and, as a result, the problem arises in that the reliability of the liquid crystal display device is lowered.
In addition, as shown in FIG. 53, in the case that the distance W1 between the sidewall of the gate electrode 108a and the sidewall of the resist film 130a becomes small with respect to the necessary width W0 of the n type impurity regions 104a, 104b, the resultant width of the n type impurity regions 104a, 104b becomes smaller than the designed value. As a result of this, the electric property of the n type thin film field effect transistor becomes different form the designed value. As a result, in the same manner as the above described case, there are some cases where the reliability of the formed liquid crystal display device is lowered.
In addition, it is considered to introduce the step of carrying out an implantation of phosphorous ions 133 in order to form the n+ type impurity regions 103a, 103b under the condition where the insulating film 137 which is processed to be a gate insulating film is not removed but rather extends to the n+ type impurity regions 103a, 103b at the time of forming a thin film field effect transistor as shown in FIG. 54. Here, FIG. 54 is another diagram for describing the conventional problem. In the case that such a step is carried out, however, the same problem as the above described problem occurs. In addition, under the condition where the insulating film 137 remains as in the above, phosphorous ions 133 need to reach the regions in which n+ type impurity regions 103a, 103b are to be formed by passing through the insulating film 137 and, therefore, the implantation energy of phosphorous ions 133 needs to be made larger, which causes the case where the resist film 130a is changed in quality through this implantation of phosphorous ions. In some cases the resist film 130a, which has been changed in quality in this manner, partially remains without being removed in the removal step of this resist film 130a. In the case that the resist film 130a remains in this manner, defects are caused such that a predetermined structure cannot be formed because of the resist film 130a which has remained in place during the following process steps, which consequently lowers the reliability of the liquid crystal display device and which lowers the yield.
This invention is provided to solve such a problem and one purpose of this invention is to provide a semiconductor device which has a high reliability and a method for the same.
Another purpose of this invention is to provide a liquid crystal display device which has a high reliability and a method for the same.
A semiconductor device according to the one aspect of this invention includes a substrate, a semiconductor film, a gate insulating film and a gate electrode. The semiconductor film is formed on the main surface of the substrate and includes the source and drain regions adjoining each other via the channel region. The gate insulating film is formed on the channel region. The gate electrode is formed on the gate insulating film and has sidewall. The gate insulating film includes an extended part which has sidewall located outside of the sidewall of the gate electrode. One of the source and drain regions include a high concentration impurity region and a low concentration impurity region of which the impurity concentration is relatively lower than this high concentration impurity region. The high concentration impurity region is formed in a region of the semiconductor film apart from the sidewall of the extended part. The low concentration impurity region is formed in a region of the semiconductor film located below the extended part.
In addition, in the semiconductor device according to the first aspect of this invention, both of the source and drain regions preferably include a high concentration impurity region and a low concentration impurity region, respectively.
By having such a structure, the position of the low concentration impurity region can be determined by using the extended part as a mask as shown in the manufacturing method described below. Then, the size (width) of this extended part is determined by partially removing the sidewall of the gate electrode by using wet etching as shown in the manufacturing method described below. Then, since the positional precision of this wet etching is sufficiently higher than the positional precision in the photolithography, which has conventionally been used for forming a low concentration impurity region, the positional precision of the low concentration impurity region can be increased. Therefore, the positional precision of the low concentration impurity region of the formed field effect transistor can be increased. As the result of this, the reliability of the field effect transistor can be increased.
In addition, in the case that an interlayer insulating film or the like is formed so as to extend from the gate electrode to the semiconductor film including the source and drain regions, a void or the like is easily created in the connection parts (corner parts) between the sidewalls of the gate electrode and the gate insulating film and the upper surface of the semiconductor film. In particular, in the case that the sidewalls of the gate electrode and the gate insulating film are located in approximately the same plane and the gate electrode and the gate insulating film form one step part, the above tendency is significant. In the present invention, however, since the extended part of the gate insulating film has already been formed in such corner parts wherein a void is the most easily created according to a prior art, the possibility where a void is created as described above can be reduced.
In addition, since a void can be prevented from being created in the corner parts formed of the sidewalls of the gate electrode and the gate insulating film and the upper surface of the semiconductor film as described above, the problem that the interlayer insulating film or the like peals due to such a void can be prevented from occurring. As a result of this, damage or an operational defect of the semiconductor device caused by such pealing of interlayer insulating film can be prevented from occurring and, therefore, the reliability of the semiconductor device can be increased.
In a semiconductor device according to the above one aspect, it is preferable for the sidewall of the extended part to be formed so as to incline with respect to the main surface of the substrate.
In this case, as shown in the manufacturing method described below, a concentration distribution so as to correspond to the inclination of the sidewall of the extended part with respect to the impurity concentration in low concentration impurity region can be formed. As a result of this, an electric field concentration can be more efficiently prevented from occurring in the low concentration impurity region.
In addition, since the sidewall of the extended part is formed so as to be inclined, at the time when an interlayer insulating film or the like is formed so as to extend from the sidewall of the gate electrode to the upper surface of the semiconductor film, the coverage of this interlayer insulating film or the like can be more improved.
In the semiconductor film according to the above one aspect, it is preferable for the gate insulating film to include an insulating film part which extends from the sidewall of the extended part to the high concentration impurity region and it is preferable for the film thickness of the insulating film part is thinner than the film thickness of the extended part or the gate insulating film.
In this case, because of the existence of the insulating film part, this insulating film part works as a protective film and, therefore, the source and drain regions can be effectively prevented from being contaminated with impurity metal or the like. As the result of this, the change of the electric characteristics of the semiconductor device due to the contamination with the impurity metal or the like in the source and drain regions can be prevented without fail and, therefore, the reliability of the semiconductor device can be more improved.
A liquid crystal display device according to the another aspect of this invention is provided with a semiconductor device according to the above first aspect.
In this case, a semiconductor device which has a high reliability can be formed as a semiconductor device in the drive circuit region or in the display pixel region of a liquid crystal display device and, therefore, the uniformity of the screen display characteristics of the liquid crystal display device can be improved. As a result of this the display characteristics of the liquid crystal display device can be improved.
In a manufacturing method for a semiconductor device according to the still another aspect of this invention, a semiconductor film is formed on the substrate. An insulating film is formed on the semiconductor film. A conductive film is formed on the insulating film. A resist film which has a sidewall is formed on the conductive film. By partially removing the conductive film through etching using the resist film as a mask, a gate electrode which has a sidewall located inside of the sidewall of the resist film is formed. By partially removing the insulating film through etching using the resist film as a mask, a gate insulating film including an extended part which has a sidewall located outside the sidewall of the gate electrode is formed. By implanting impurities into the semiconductor film by using the resist film as a mask, a high concentration impurity region for one of the source and drain regions are formed in a region of the semiconductor film apart from the sidewall of the extended part. At this time, high concentration impurity regions may be formed respectively in the source and drain regions. Then the resist film is removed. After the step of removing the resist film, by implanting impurities to the semiconductor film using the gate electrode as a mask, a low concentration impurity region for one of the source and drain regions of which the impurity concentration is comparatively lower than that of the high concentration impurity region is formed in regions of the semiconductor film located below the extended part. At this time, low concentration impurity regions may be formed respectively in the source and drain regions.
Here, the distance (receding amount of the sidewalls of the gate electrodes) from the positions of the sidewalls of the resist film to the positions of the sidewalls of the gate electrode in the step of forming the gate electrode corresponds to the size (width) of the extended parts of the gate insulating film which extend from the sidewalls of the gate electrode to the outside. Then, this receding amount of the sidewalls of the gate electrode can be controlled with high precision through isotropic etching. Therefore, the size (width) of the extended parts of the gate insulating film can be determined with high precision. Then, since the low concentration impurity regions are formed by using gate electrode as a mask, the distance (width of the extended parts) between the sidewalls of these extended parts and the sidewalls of the gate electrode becomes approximately equal to the width of the regions where the low concentration impurity regions are formed. As a result, the dimensional precision of the low concentration impurity regions can be improved in comparison with the conventional case where the resist film is used as a mask. Therefore, the electric characteristics of the formed field effect transistor can be prevented, without fail, from fluctuating due to the fluctuation of the dimension of the low concentration impurity region. As a result of this, the reliability of the semiconductor device can be improved.
In addition, the resist film which has been used at the time of forming the gate electrode can again be used as a mask at the time of forming the high concentration impurity region and, therefore, the step can be simplified in comparison with a conventional case where a resist film is newly formed so as to be used as a mask for forming these high concentration impurity region.
In a manufacturing method for a semiconductor device according to the further aspect of this invention, a semiconductor film is formed on the substrate. An insulating film is formed on the semiconductor film. A conductive film is formed on the insulating film. A resist film which has a sidewall is formed on the conductive film. By partially removing the conductive film through etching using the resist film as a mask, gate electrode which have sidewall located inside the sidewall of the resist film are formed. By partially removing the insulating film through etching using the resist film as a mask, a gate insulating film including extended part which have sidewall located outside the sidewall of the gate electrode is formed. The resist film is removed. By implanting impurities into the semiconductor film using the gate insulating film as a mask, a high concentration impurity region for one of the source and drain regions is formed in the region of the semiconductor film apart from the sidewall of the extended part. At this time, the high concentration impurity regions may be formed respectively in the source and drain regions. Then, by implanting impurities into the semiconductor film by using the gate electrode as a mask, a low concentration impurity region for one of the source and drain regions of which the impurity concentration is comparatively lower than the high concentration impurity region are formed in the region of the semiconductor film located below the extended part. At this time, the low concentration impurity regions may be formed respectively in the source and drain regions.
In this manner, in the same way as the manufacturing method for a semiconductor device in the above still another aspect, the dimension of the extended part of the gate insulating film which extend from the sidewall of the gate electrode to the outside can be determined with an excellent precision. Then, since the width of the low concentration impurity region corresponds to the width of the extended part of the gate insulating film which extend from the sidewall of the gate electrode to the outside, it becomes possible to determined the width of the low concentration impurity region with an excellent precision. Therefore, a problem can be prevented from occurring that the electric characteristics of the semiconductor device such as field effect transistor, which include these low concentration impurity region, fluctuate due to the change of the width of the low concentration impurity region. As a result of this, the reliability of the semiconductor device can be improved.
In addition, since a gate insulating film is used as a mask at the time of forming the high concentration impurity region, it is not necessary to form a resist film so as to be used as a mask at the time of forming the high concentration impurity region such as in a prior art. As a result of this, the manufacturing method for the semiconductor device can be simplified.
In addition, since a resist film is not used as a mask at the time of forming the high concentration impurity region and low concentration impurity region, the resist film which is used as a mask will not change in quality by receiving the implantation of impurities. Therefore, a problem can be prevented from occurring that the resist film of which the quality has changed remain so that a predetermined structure can not be gained and the yield of products is lowered.
In the above described manufacturing method for a semiconductor device according to the further aspect, it is preferable to carry out the step of forming high concentration impurity regions and the step of forming low concentration impurity regions simultaneously.
In this case, the manufacturing method for a semiconductor device can be more simplified.
In the above described manufacturing method for a semiconductor device according to the still another and the further aspects, it is preferable to make remain an insulating film part, which has the film thickness thinner than the film thickness of the extended part of the gate insulating film, on the semiconductor film which is to become the high concentration impurity region in the step of forming a gate insulating film.
In this case, the insulating film part can be utilized as a protective film which prevents impurities such as impurity metals from entering into the high concentration impurity region. Therefore, a problem can be prevented, without fail, from occurring that the electric characteristics of the semiconductor device fluctuate due to the existence of such an impurity metal in the high concentration impurity region. As a result of this, the reliability of the semiconductor film can be more improved.
In the manufacturing method for a semiconductor device according to the above still another and further aspects, it is preferable for the impurities implanted to the low concentration impurity regions and high concentration impurity regions to be n type conductive impurities and it is preferable for the gate electrodes, the gate insulating film and the source and drain regions to form n type thin film field effect transistors. Prior to the step of forming the gate electrodes of the n type thin film field effect transistors, it is preferable to further include the step of forming the implemented p type thin film field effect transistor. In the step of forming the p type thin film field effect transistor, preferably a resist film is formed of the conductive film. By partially removing the conductive film using the resist film as a mask, the gate electrode of the p type thin film field effect transistor is formed and at the same time a conductive film is made to remain on the region where the n type thin film field effect transistor is to be formed. By using, as a mask, the gate electrode of the p type thin film field effect transistor and the conductive film which has been made to remain on the region where the n type thin film field effect transistor is to be formed, p type conductive impurities are implanted into the semiconductor film and, thereby, one of the source and drain regions of the p type thin film field effect transistor is formed. At this time, both of the source and drain regions may be formed.
Here, when the case where n type thin film field effect transistor is formed in advance and after that p type thin film field effect transistor is formed is taken into consideration, it is necessary to form a resist film so as to cover the n type thin film field effect transistor which has already been formed at the time when the step of forming one of the source and drain regions of the p type thin film field effect transistor is carried out. This is to prevent the electric characteristics of the n type thin film field effect transistor from changing due to the implanted p type conductive impurities. In the case that p type thin film field effect transistor are formed in advance as in the above, however, a conductive film remains on the regions where n type thin film field effect transistor is to be formed at the time when p type conductive impurities are implanted and this remaining conductive film is used as a mask and, therefore, the step of forming a resist film as a mask can be omitted. As a result of this, the manufacturing method can be designed to be simplified.
In the manufacturing method for a semiconductor device according to the above described still another and further aspects, it is preferable for the sidewall of the extended part to be formed so as to incline with respect to the main surface of the substrate in the step of forming a gate insulating film.
In this case, in the step of forming low concentration impurity region, the impurity concentration in the low concentration impurity region can be changed corresponding to the inclination of the sidewall of the extended part of the gate insulating film. That is to say, the impurity concentration can be made high comparatively in the region of the semiconductor film located below the part of which the film thickness of the extended part is comparatively thin because of the inclination of the sidewall of the extended part while the impurity concentration can be made comparatively low in the region of the semiconductor film beneath the part of which the film thickness of the extended part is comparatively thick. In this manner, the graduation of the impurity concentration can be formed in the low concentration impurity region so that the change of the electric field intensity in the low concentration impurity region can be made more gentle. As a result of this, the electric field concentration can be prevented from occurring so that a problem can be prevented from occurring where the semiconductor device malfunctions due to this electric field concentration. As a result, the reliability of the semiconductor device can be more improved.
In the manufacturing method for a semiconductor device according to the above described still another and further aspects, by partially removing an insulating film through isotropic etching in the step of forming a gate insulating film, it is preferable to incline the sidewall of the extended part with respect to the main surface of the substrate.
In this case, the sidewall of the extended part can be easily inclined with respect to the main surface of the substrate.
In the manufacturing method for a semiconductor device according to the still another and further aspects, it is preferable to incline the sidewall of the extended part with respect to the main surface of the substrate by using a resist receding method in the step of forming a gate insulating film.
In this case, the rate of the resist film being removed through etching can be changed by setting the manufacturing method conditions so as to modify the etching rate of the resist film. Therefore, the etching time of the part which is to become sidewall of the extended part of the insulating film can be modified by changing the rate of the resist film being removed. Thereby, the inclination angle of the sidewall with respect to the main surface of the substrate can be modified. As a result of this, it becomes possible to freely set the angle formed between the sidewall of the extended part and the main surface of the substrate.
In the manufacturing method for a liquid crystal display device according to the still further aspect of this invention, the manufacturing method for a semiconductor device according to the above described still another or further aspects is used.
In this manner, a semiconductor device which is used in the drive circuit or for display pixel of the liquid crystal display device can be easily formed so as to have high reliability. As a result of this, a liquid crystal display device which indicates stable display characteristics can be gained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.